1. Introduction
This invention relates to a method for selective metal deposition. More particularly this invention relates to a method for depositing metal onto a substrate in a pattern such as lines and spaces as required for the fabrication of electronic circuits. The invention is especially useful for formation of microelectronic circuits having submicron dimensional features.
2. Description of the Prior Art
Electronic circuits comprise an array of conductive lines and spaces over an insulating substrate such as a plastic or ceramic. There are many methods for the manufacture of electronic circuits. A conventional method for making circuits comprises the formation of printed circuit boards by a subtractive process. In the subtractive process, typically a planar plastic substrate having copper foil cladding on both of its surfaces is drilled to provide openings passing between the surfaces. The walls of the openings are subsequently metallized, typically by an electroless metal deposition process whereby there is provided conductive pathways electrically connecting the two surfaces of the circuit board. Thereafter, a photosensitive organic coating is coated over the copper foil cladding. Ultraviolet exposure followed by development produces a desired imaged pattern of traces and alternating with spaces. Exposed copper in the spaces may then be reinforced with electrolytic copper and subsequently solder or another dissimilar metal or organic etch resist is then coated onto all exposed copper surfaces. The organic coating is selectively removed and the copper exposed by removal of the organic coating is etched with a chemical etchant to provide a conductive circuit pattern on the plastic substrate. The circuit board manufactured by this method comprises a circuit having lines and spaces typically of a width of several mils.
Another method for formation of a circuit board is known in the art as an additive process. In this process, an unclad substrate is drilled to provide openings between surfaces. Thereafter, the entire surface of the substrate is prepared for metal plating by immersion in an electroless plating catalyst solution such as a palladium tin colloid catalyst as disclosed in U.S. Pat. No. 3,011,920. Following catalysis, an organic coating in an image pattern of lines and spaces is provided on the entire surface of the plastic substrate. By providing recesses within the organic coating, plating catalyst is exposed and available to initiate a metal deposition reaction. The substrate is then immersed in an electroless metal plating solution for a time sufficient to metallize to a full desired thickness. Thereafter, the organic coating may be removed if desired and catalyst exposed by the removal of the organic coating may be removed by contact with a suitable stripper. Though methods for formation of additive circuits have been known for many years, most circuits are made by the subtractive process due to the unsuitability of metal plating solutions capable of providing adequate thick deposits of metal having suitable metallurgical properties within a reasonable acceptable period of time. Boards produced by this method have lines and spaces of a width at least comparable to the line widths obtained by subtractive processes and often exceeding that possible by subtractive methods due to elimination of undercut during an etching step.
Another method for formation of circuits is known in the art as a semi-additive method and is designed to minimize a limitation in resolution caused by undercutting. In this method, a board is provided with a thin clad copper coating which can then be built up by conventional plating procedures. The semi-additive method is essentially a combination of the subtractive and additive methods. Each of the methods is described by Coombs, Printed Circuits Handbook, McGraw-Hill Book Company, New York, 2nd Ed., 20-3 to 23-19, 1979, incorporated herein by reference.
There is a desire in the industry to provide circuits of lines and spaces of finer dimension than those possible or obtainable by the methods described above. For example, in printed circuit board manufacture, it is desirable to reduce lines and space widths to one mil or less. This desire is discussed by R.D. Rust, "Fine Line Technology, The Impact of Dry Plasma Processing," P.C. Fab., June 1987, pp. 37-44. For formation of circuit patterns over ceramics or silicon based substrates, such as in the formation of integrated circuits, it is desirable to reduce line width and spaces to one micron or less.
An example of an effort to obtain fine line image resolution over a nonconductive or semiconductive substrate is disclosed by Kenji et al, Japan Kokai Tokyo Koho J.P. 62,250,177 [87,250,177] Oct. 31, 1987, application 86/92,536,22, April 1986. In this method, a fine metal pattern is formed on an electrically insulating or semiconductive substrate by selective deposition in an electroless coating bath containing sodium hypophosphite as a reducing agent. The substrate is precoated with a catalytic pattern before dipping into the bath. Thus, a palladium coated polyimide board is capable of masking with a resist pattern and dipping in a bath containing nickel sulfate, a source of tungsten ions and a hypophosphite reducing agent to provide a fine image pattern of nickel-tungsten-phosphorous alloy.